Computer control unit capable of dynamically reinterpreting instructions

ABSTRACT

A microprogrammed computer is disclosed in which two sets of microprograms, each set containing a microprogram to execute each program instruction, are stored in microprogram memory. A selected program instruction is provided which, when executed, changes the set of microprograms from which particular microprograms are selected to execute subsequent program instructions. Insofar as the microprograms comprising the newly selected set of microprograms differ, in general, from the corresponding microprograms comprising the previously selected set, the execution characteristics of subsequent program instructions executed by microprograms in the newly selected set are changed.

United States Patent Senese 1 Dec. 25, 1973 [54] COMPUTER CONTROL UNITCAPABLE OF 3,544,969 12/1970 Rakoczi 340/1725 3,614,740 l0/l971 Delagi340/1725 DYNAMXCALLY REINTERPRETING INSTRUCTIONS Primary Examiner-RaulfeB. Zache Att0meyW. L. Keefauver et a].

[57] ABSTRACT A microprogrammcd computer is disclosed in which two setsof microprograms, each set containing a microprogram to execute eachprogram instruction, are stored in microprogram memory. A selectedprogram instruction is provided which, when executed, changes the set ofmicroprograms from which particular microprograms are selected toexecute subsequent program instructions. insofar as the microprogramscomprising the newly selected set of microprograms differ, in general,from the corresponding microprograms comprising the previously selectedset, the execution characteristics of subsequent program instructionsexecuted by microprograms in the newly selected set are changed.

5 Claims, 5 Drawing Figures CONTROL UNlT 2 INSTRUCTION DATA REGISTERMEMORY MlCRO- MEMORY INSTRUCTION SEGMENT SEGMENT OPERAND HELD HELDLOCATION FIELD I (OPCODE) FIELD j l J 7 a 9 1O 11 t 18 14 I MICRO- wMAIN 19 MEMORY 2. TlMING ClRCUIT T MICROPROGRAM STATEMENT -s ADDRESSDECODER PATENTED 3.781 .823

SHEEI 1 (IF 2 FIG. 1

PRTOR ART 7 MAIN MEMORY INPUT-OUTPUT CONTROL ARTTNMETIO UNIT UNIT UNIT LL FIG. 2 1 2 w INSTRUCTION OATA REGISTER MEMORY MICRO- MEMORYINSTRUCTION SEGMENT ggfgk FIELD FIELD (OP CODE) FIELD 6 8 9 10 11 2 1814 I MICRO- MAW PROGRAM 19 MEMORY MEMORY N. TTM|NG 20 CIRCYUIT MTGRORROGRAM STATEMENT -5 AOORESS OEOOOER FIG. 3 MIGROPROGRAM MEMORYSEGMENT S SEGMENT S2 SEGMENT S J SEGMENT S SEGMENT S PATENTEB 05825 I975F/G. 4A

FIG. 4B

SHEET 2 BF 2 LDGRTTDN ADDRESS MTGRDPRDGRRM MEMDRY CONTENTS MEMDRY MEMDRYSEGMENT MICROINSTRUCTION SEGMENT CODE LDGRTTDN FIELD FIELD LDGRTTDN GDDEW V V k V FIELD 5 SE, M1 S SL3 T N G s51, f; 82 SL1 i EA S2 SL2 m um 3SL MI5 S SE 1E7 S NTEI i 1 ii;

3 3L8 MIG E s SE,

S SLN LDGRTTDN ADDRESS MTGRDPRDGRRM MEMDRY GDNTENTS MEMDRY MEMDRYSEGMENT MTGRDTNSTRDGTTDN SEGMENT LDGATTDN FIELD HELD LDGRTTDN CODE 1 w AA i FIELD J+1 1 M l i a? 3J+2MV-LV3 S SLNTMM M1 Sf SJ+2 SL3 MI5 3L3 SL83J+3 Q G SM S SE, PM

SM SLN 1 COMPUTER CONTROL UNIT CAPABLE OF DYNAMICALLY REINTERPRETINGINSTRUCTIONS BACKGROUND OF THE INVENTION 1. Field of the Invention Thisinvention relates to the field of digital computer control units and,more specifically, to digital computer control units of themicroprogrammed type.

2. Description of the Prior Art In a digital computer having amicroprogrammed control unit, hereafter referred to as a microprogrammedcomputer, the first step in executing a particular program instructionis the determination of which microprogram is to be used for thatprogram instruction. As used herein, the phrase "program instruction"refers to an instruction in a language at the lowest level of complexitynormally used for programming, typically referred to as object orassembly language. Following the determination of the correctrnicroprogram, the first microinstruction in the microprogram isexecuted. Thereafter, each microinstruction in the microprogram isexecuted in the appropriate order until all such microinstructions havebeen executed. All of the operations performed in the execution of allof the microinstructions in the microprogram constitute the executioncharacteristics of the program instruction. Absent some means forvarying the microinstructions comprising the microprogram for a programinstruction. the execution characteristics of a program instruction arealways the same.

Some methods have been developed for altering the executioncharacteristics of program instructions by altering themicroinstructions executed as part of the respective microprograms. Inthe application of these methods the execution characteristics ofprogram instructions are generally altered by selectively setting thestates of memory devices affecting the determination of whichmicroinstruction in the microprogram is to be executed next. Forexample, a conditional branch within a microprogram may be effectedduring execution of the microprogram by combining selected address datacontained within one microinstruction with data contained in selectedmemory devices, the states of which have been preset, to determine theaddress of the next microinstruction to be executed. The result of theconditional branch is the selection of one of a plurality ofmicroinstructions for execution. While such methods are useful in manyapplications, they can be cumbersome and possibly inefficient when theexecution characteristics of most or all of the program instructions areto be altered. This is particularly true if the alteration is of ageneral nature and is a common alteration for all program instructions.One such common alteration would be the removal of all'checkingoperations from the execution of all program instructions in order tospeed execution.

SUMMARY OF THE INVENTION In a control unit according to applicant'sinvention, the execution characteristics of all program instructions maybe altered by the execution of a single program instruction. Morespecifically, according to applicant's invention, two sets ofmicroprograms are stored in selected portions of microprogram memory.Each set contains one microprogram for executing each programinstruction in the set of program instructions. A

program instruction is provided which, when executed, modifies amicroinstruction selection address code used in determining from whichof the two sets of microprograms the microprograms for executing programinstructions are to be taken. The altering of this address code changesthe set of microprograms from which the microprograms to executesubsequent program instructions are selected. As a result, the executioncharacteristics of program instructions executed subsequently aredetermined by the microprograms in the newly selected set ofmicroprograms.

It is an object of applicants invention to provide a digital computercapable of changing the execution characteristics of its programinstructions.

It is another object of applicants invention to provide a digitalcomputer control unit responsive to a selected program instructionwhich, when executed, modifies the selection of microprogramsdetermining the execution characteristics of all subsequent programinstructions.

It is yet another object of applicant's invention to provide a digitalcomputer control unit responsive to the execution of a selected programinstruction to change a selection code determining the set ofmicroprograms from which the microprograms to execute subsequent programinstructions are selected.

DESCRIPTION OF THE DRAWING FIG. 1 shows a block diagram of a computer;

FIG. 2 shows a block diagram of the control unit and main memory shownin FIG. I;

FIG. 3 shows a representation of the segmentation of microprogrammemory; and

FIGS. 4A and 4B are representations of example microprograms stored inmicroprogram memory.

DETAILED DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENT As was indicatedabove, applicants invention is directed at an improvement inmicroprogrammed computers. To fully appreciate the operation ofapplicants invention it is first necessary to understand in general thefunction of a control unit in a digital computer. A representation inblock diagram form of a general digital computer is shown in FIG. 1.Many variations ofthis basic structure are possible. However, thestructure shown in FIG. I is adequate to represent the general functionsofa control unit. Specifically, the control unit I accepts andinterprets instructions stored in the main memory 2. Pursuant to thoseinstructions, the control unit I controls the operations of the otherunits of the computer while directing the flow of information betweenthose units. More specifically, control unit 1, in response to programinstructions transmitted to the control unit 1 from the main memory 2,sequences the operations and information flow between and, to someextent, within the arithmetic unit 4, the main memory 2, and theinput-output unit 3. Insofar as the function of the control unit is tocontrol the flow of information and the occurrence of operations withinthe computer. the control signals from the control unit occur in asequence. In a microprogrammed control unit the proper sequencing ofcontrol signals isobtained by executing predetermined sequences ofmicroinstructions, each one of which directs or in some way affects theinformation in the computer and the flow of that information within andbetween the elements of the computer.

It is useful here to clarify the meaning of a microinstruction asopposed to a program instruction. It should be observed that a programinstruction is generally of the type used by a programmer in specifyingthe algorithms he wishes the computer to perform. The programmer isgenerally unconcerned with the specifics of how the computer performseach step, such as addition or multiplication, in the algorithm. Thus, aprogram instruction is considered the lowest level instruction withwhich a programmer is concerned. A microinstruction, however, is simplerin most instances than a program instruction. In fact, the execution ofa program instruction generally requires a plurality ofmicroinstructions. A microinstruction, for example, may gate thecontents of a register in the arithmetic unit on to a data bus.Thereafter. another microinstruction may gate the information from thedata bus into another register in the arithmetic unit or in another unitof the computer. Microinstructions can be considered to controlmicrooperations which are, in general, of little or no concern to theprogrammer.

Referring now specifically toapplicants invention, the control unit 1 ofFIG. I is expanded in FIG. 2 and several of its pertinent majorcomponents are shown therein in block diagram form. It should first benoted that an MPM, microprogram memory, 6 is shown in FIG. 2 ascontained in control unit 1. The MPM 6 stores the microprogram used toexecute each of the program instructions. The output, to be describedshortly, of the MPM 6 on the lines l7, l8, and I9 is supplied toselected fields in the lDR, instruction data register, 7. It should benoted that the program instructions comprising the output of the mainmemory 2 on the lines 13 and 14 are also supplied to selected fieldsofthe lDR 7. Thus, the lDR 7 not only receives the out put from the MPM6, containing microinstructions, but it also receives programinstructions from the main memory 2. The significance of the dualfunction of the lDR 7 will be seen in the discussion which follows.

Returning to the discussion of the MPM, microprogram memory, 6 (FIG. 2),it can be seen in FIG. 3 that it is divided into M segments. Each ofthese segments contains N locations. The address for a unique locationin the microprogram memory, therefore, consists of two portions, thefirst being a segment code specifying in which segment ofthe MPM thelocation appears and the second being a segment location code specifyingwhich location within the particular segment is the desired location.The use of these two codes will also be developed further below.

Each location in the MPM, microprogram memory, 6 (FIG. 3) stores whatshall be referred to as a microprogram statement. This is to bedistinguished from a microinstruction since a particular microprogramstatement includes not only a microinstruction but also the address ofthe next microprogram statement in the microprogram in which bothmicroprogram statements are contained. The address of the nextmicroprogram statement includes a memory segment code and a memorysegment location code. It should be noted that, as the precedingdiscussion suggests, microprograms are stored in the MPM 6 in a linkedlist structure which is well known in the prior art.

The structure of a microprogram statement just described is reflected inthe fields of the lDR, instruction data register, 7 (FIG. 2) to whichthe outputs of the MPM, microprogram memory, 6 are supplied.Specifically, the microinstruction contained in a microprogram statementis supplied on the line 17 to the microinstruction field 8 of the lDR 7.In addition, the output of the MPM 6, consisting of the memroy segmentcode for the address of the next microprogram statement, is supplied onthe line 18 to the memory segment field 9 of the IDR 7. Finally, theoutput of the MPM 6, consisting of the memory segment location code forthe address of the next microprogram statement, is supplied on the line19 to the memory segment location field 10 of the lDR 7. It should benoted that the fields 9 and 10 (FIG. 2) comprise what can be considereda next address field whose contents specify the address of the nextmicroprogram statement in the current microprogram.

Having discussed the linked list structure of microprograms stored inthe MPM 6 (FIG. 2) and the outputs of the MPM 6 to the lDR 7, attentionis turned to the outputs of the main memory 2 and their effect on thelDR 7. In FIG. 2 it can be seen that the output of the main memory 2 online 14 is supplied to the memory segment location field 10 of theinstruction data register 7. The output from the main memory 2 on theline 14 is the operation code, or OP code, for the program instructionto be executed. Thus, when a program instruction is loaded from mainmemory into the lDR 7, the OP code of that instruction is loaded in thememory segment location field 10. The remaining portion of the programinstruction, more specifically, the operand, is loaded by means of theline 13 into the operand field 11.

It was previously mentioned that the memory segment field 9 (FIG. 2) andthe memory segment location field I0 of the lDR, instruction dataregister, 7, are to be considered the next address field of the lDR 7.The outputs of those two fields on the lines I6 and I5, respectively,are supplied to the MSAD, microprogram statement address decoder, 5.When a new address, consisting of the contents of the fields 9 and It](FIG. 2) of the lDR 7, is supplied to the MSAD 5, the address is decodedand the appropriate microprogram statement stored in the microprogrammemory 6 is accessed to be supplied at the appropriate time to the lDR7. Timing of operations within the control unit I is controlled by thetiming circuit 20.

Having now described generally the structure of the control unit 1 (FIG.2) and its relationship to the main memory 2, attention is turned todiscussion of the function of this control unit 1 in relation toapplicant's invention. It will be recalled that an object of applicant'sinvention is to provide a microprogrammed computer which can change theexecution characteristics of its program instructions. Pursuant to thisobjective the MPM, microprogram memory, 6 contains two complete sets ofmicroprograms, each set containing one microprogram for each programinstruction. Referring to FIG. 3 the first set of microprograms isstored in the memory segments indicated by memory segment codes S,through 8,. The second set of microprograms is stored in the segmentswith memory segment codes S through 8 Furthermore, the firstmicroprogram statement in each microprogram in the first set ofmicroprograms is stored in the segment corresponding to segment code S,at the location corresponding to the OP code of the program instructionassociated with that microprogram. More specifically, the OP code ofeach program instruction specifies the segment location code for thefirst microprogram statement in the microprogram to execute that programinstruction. In the case of microprograms contained in the first set ofmicroprograms, that first microprogram statement is stored in thesegment corresponding to segment code 5,. Similarly, for microprogramscontained in the second set of microprograms, the first microprogramstatement is stored in the location corresponding to the OP code of theappropriate program instruction in the segment corresponding to thememroy segment code hh It was previously mentioned that the contents ofthe next address field in the IDR, instruction data register, 7 (FIG. 2)consisting of the memroy segment field 9 and the memory segment locationfield l0, specify the address of the next microprogram statement to beread from microprogram memory 6 into the IDR 7. To execute amicroprogram for a program instruction, however, it is first necessaryto obtain the address of the first microprogram statement in themicroprogram for that program instruction. As was noted above, the firstmicroprogram statement of each microprogram in the first set ofmicroprograms appears in the location corresponding to the OP code ofthe program instruction in the memory segment corresponding to thesegment code 8,. Therefore, if the memory segment field 9 (FIG. 2) ofthe IDR 7 contains the code 5,, the loading of the OP code of theprogram instruction to be executed into the memory segment locationfield completes the address of the first microprogramstatement in theappropriate microprogram in the first set of microprograms. As a result,the MSAD, microprogram statement address decoder, 5 decodes that firstaddress and accesses microprogram memory 6 resulting in the loading ofthe appropriate microprogram statement into the fields 8, (FIG. 2), 9,and ll) of the IDR 7. It should be noted, however, that if the memorysegment field 9 (FIG. 2) contains the memory segment code S the addressdecoded by the MSAD 5 when the program instruction is loaded from mainmemory 2 into the IDR, instruction data register, 7 is the address ofthe first microprogram statement in the appropriate microprogramcontained in the second set of micropro grams. As a result, changing thesegment code in the field 9 prior to decoding the first microprogramstatement address for a program instruction has the affect of changingthe microprogram selected to execute that program instruction.Therefore, it is the code stored in the memory segment field 9 (FIG. 2)which is affected by the previously mentioned program instruction forchanging the execution characteristics of subsequent programinstructions.

To fully illustrate the operation of the control unit 1 in conjunctionwith what will be called the change characteristics" programinstruction, an example illustrating the effects of the changecharacteristics program instruction on another instruction will bediscussed below. It is assumed for this example that the 0? code for thechange characteristics program instruction is SL and the OP code for theexample program instruction is SL It is further assumed that the field 9(FIG. 2) of the IDR 7 contains the segment code S when the main memory 2loads the example program instruction having OP code SL and operandOPER, into the fields l0 and II, respectively. Insofar as the segmentcode S, and the segment location code SL,, the OP code of the programinstruction, together constitute a valid address, the MSAD 5 (FIG. 2)decodes that address and accesses the appropriate microprogramstatement. The statement accessed is included in the representation ofmicroprogram memory shown in FIG. 4A. As can be seen therein, thestatement stored at the address corresponding to the segment code S andsegment location code SL,, referred to as address 8,, SL,, contains themicroinstruction Ml the segment code S, and the segment location code SLThis statement is loaded into instruction data register 7 (FIG. 2) withthe microinstruction MI being loaded into the field 8, the memorysegment code S, being loaded into the field 9, and the memory segmentlocation code SL being loaded into the field 10.

Since the valid microinstruction MI, has been loaded into themicroinstruction field 8 (FIG. 2) of the IDR 7, that microinstruction isexecuted. Following its execution the MSAD, microprogram statementaddress de coder, 5 decodes the contents of the fields 9 and 10,consisting of the codes S and SL;,, respectively, to determine theaddress of the next microprogram statement in the current microprogram.When the codes in the fields 9 and 10(FIG. 2) are decoded, themicroprogram statement corresponding to the address, referred to as S SLis accessed and loaded into the IDR 7. Referring to FIG. 4A, it can beseen that the microprogram statement corresponding to the address 5,, SLcontains the microinstruction M1 The memory segment code S and thememory segment location code SL As illustrated above, when thismicroprogram statement is loaded into the IDR 7 (FIG. 2), themicroinstruction Ml, is executed, whereupon the MSAD 5 decodes theaddress S SL and accesses the appropriate microprogram statement. Whenthe microprogram statement corresponding to the address S SL, isthereafter loaded into the IDR 7 (FIG. 2), the microinstruction MI:(FIG. 4A) is loaded into the microinstruction field 8 (FIG. 2) and isexecuted. In addition, the segment code 8;, (FIG. 4A) is loaded into themem ory segment field 9 (FIG. 2), and the segment location code SL (FIG.4A) is loaded into the memory segment location field 10 (FIG. 2).

After the microinstruction MI, is executed, the microprogram statementcorresponding to the address 5,, SL is accessed by the MSAD 5 and isloaded into the IDR, instruction data register, 7 (FIG. 2). In thiscase, however, referring to FIGv 4A, it can be seen that themicroprogram statement stored in the location having the address S SLcontains the microinstruction MI The microinstruction MI, is the commandto load a new program instruction from main memory 2 (FIG. 2) into thefields I0 and II of the IDR 7. As it would be expected, this indicatesthe completion of the execution of the current microprogram. In fact,the final microprogram statement in every microprogram contains themicroinstruction MI Insofar as the microprogram statement stored inlocation having the address S SL (FIG. 4A) is the last microprogramstatement in the microprogram for executing the current programinstruction, it is of interest to note that the statement contains amemory segment code even though there is no additional microprogramstatement in the microprogram. Specifically, as can be seen in FIG. 4A,the memory segment field of the microprogram statement contained in thelocation having the address S SL contains the code 5,. Thus, when themicroprogram statement is loaded into the IDR 7 (FIG. 2), the memorysegment field 9 is loaded with the code 8,. As a result, the nextprogram instruction loaded into the fields l and 11 of the IDR 7 will beexecuted using the appropriate microprogram in the first set ofmicroprograms. More specifically, it will be recalled that the presenceof the code 8, in the field 9 at the time a program instruction isloaded into the IDR 7 results in the location of the first microprogramstatement being contained in the memory segment corresponding to thesegment code 8,. This necessarily implies that the microprogram to beused to execute the new program instruction is contained within thefirst set of microprograms.

It has been seen above that when a program instruction which is not thechange characteristics program instruction is executed using amicroprogram in the first set of microprograms, the field 9 (FIG. 2)contains the code S, at the completion of the execution of thatmicroprogram. Since the field 9 contains the code 5,, the next programinstruction executed will also be executed by a microprogram in thefirst set.

It is now of interest to consider the results if the changecharacteristics program instruction is executed next. The OP code forthis program instruction is assumed to be SL When this OP code is loadedinto the field (FIG. 2) by the main memory 2, the MSAD S decodes thecontents of the fields 9 and 10, specifically, the codes 8, and SL,,,respectively, and accesses the corresponding microprogram statement inthe microprogram memory (FIG. 4A). As can be seen in FIG. 4A themicroinstruction for the microprogram statement stored at address 8,,SL, is the microinstruction Ml It has already been seen that this is themicroinstruction which commands the loading of a new program instructioninto the IDR, construction data register, 7 (FIG. 2). MOreover, itindicates the termination of the microprogram for the current programinstruction which, in this case, is the change characteristicsinstruction. Therefore, the single microprogram statement stored ataddress 8,, SL,,, (FIG. 4A) comprises the entire microprogram for thechange characteristics instruction in the first set of microprograms.

There is, however, an additional point to note about the microprogramstatement stored at address 8,, SL,,- (FIG. 4A). As mentioned earlier, amicroprogram contained in the first set of microprograms for executing aprogram instruction which is not the change characteristics programinstruction has in its final microprogram statement not only themicroinstruction M1,, but also the memory segment code 8,. This is notthe case, however, when the program instruction is the changecharacteristics program instruction. Referring to FIG. 4A, it can beseen that the microprogram statement stored at address 5,, SL,, containsin its memory segment field the code Sm. As a result, when, in theexecution of the change characteristics program instruction, thismicroprogram statement is loaded into the IDR 7 (FIG. 2), the memorysegment field 9 is loaded with the code S As a further result, when thenext program instruction is loaded into the instruction data register 7from the main memory 2 pursuant to the microinstruction MI the locationof the first microprogram statement in the microprogram for executingthe new program instruction is contained in the memory segmentcorresponding to the code 8 It will be recalled that all microprogramstatements appearing in that memory segment are the beginningmicroprogram statements for microprograms in the second set ofmicroprograms. Thus, the microprogram used to execute the next programinstruction will be contained in the second set of microprograms.

To fully illustrate the effect of having executed the changecharacteristics program instruction, the execution at this point of theexample program instruction having the OP code SL, will be discussed. Itwill be recalled that this is the same program instruction which wasdiscussed prior to the execution of the change characteristics programinstruction.

Having loaded the OP code SL, into the memory seg ment field 10 (FIG. 2)from main memory 2, the MSAD S decodes the contents of the fields 9 and10, specifically, codes 8 and SL,, respectively, and accesses theappropriate microprogram statement shown in FIG. 4B. As can be seentherein the microprogram statement stored at address 3 SL, contains themicroinstruction Ml,, the memory segment code 8 and the memory segmentlocation code SL This microprogram statement is loaded into the IDR 7(FIG. 2), and the microinstruction MI, is executed. Thereafter, the MSAD5 decodes the address 5H4, 8L, and accesses the correspondingmicroprogram statement. It can be seen in FIG. 48 that the microprogramstatement for the address S SL contains the microinstruction Mi thememory segment code S and the memory segment location code SL Again,following the loading of this microprogram statement into the IDR 7(FIG. 2), the microinstruction MI, is executed and the next address isdecoded. In this case, the next address S 5L, (FIG. 48) contains themicroinstruction Ml and the segment code S As has been seen before, themicroinstruction M1,, indicates that this is the final microprogramstatement in the microprogram. It should, however, be noted that thesegment code which is contained in the microprogram statement and whichis loaded into memory segment field 9 (FIG. 2) of the IDR 7 is the codeS Thus, the address of the first microprogram statement in themicroprogram to execute the next program instruction loaded into theinstruction data register 7 will be contained in the memory segmentcorresponding to the segment code S As seen before, this necessarilyimplies that the next program instruction will also be executed by amicroprogram in the second set of microprograms. It should be noted herethat the segment code contained in the final microprogram statement ofevery microprogram in the second set of microprograms except themicroprogram for the change characteristics instruction is the segmentcode 1+,-

It has been seen above that when the program instruction having the OPcode SL, is executed by a microprogram contained in the first set ofmicroprograms the sequence of microinstructions executed is thefollowing: MI,, MI,,, M1,, and MI,,. After having executed the changecharacteristics" program instruction, however, the same programinstruction having the OP code SL, is executed by a microprogramcontained in the second set ofmicroprograms. In that case the sequenceof microinstructions executed is the following: M1,, M1,, and M1 It isreadily apparent that the microinstruction MI, is eliminated in theexecution of the program instruction having the OP code SL, using themicroprogram in the second set of microprograms. Thus, in thissituation, it would be expected that the program instruction is executedfaster when executed by the microprogram in the second set ofmicroprograms.

It should also be noted that the above discussion has described thefunction of the change characteristics program instruction with respectto changing from the first set of microprograms to the second set ofmicroprograms. The process may easily be reversed, however, merely byexecuting another change characteristics program instruction.Specifically, it will be recalled that when the program instructionhaving the OP code SL was last executed, the memory segment code S, wasloaded into the memory segment field 9 (FIG. 2) along with themicroinstruction M1 in the field 8. Thus, if the change characteristicsprogram instruction, having the OP code SL is loaded next into theinstruction data register 7 (FIG. 2), the MSAD 5 accesses the locationSJ+h SL It can be seen in FIG. 48 that this location contains themicroinstruction M1 requiring the loading of the next programinstruction, and the segment code 8,. As a result of the loading of thesegment code S, into the memory segmentfield 9 (FIG. 2) ofthe IDR 7, thenext program instruction loaded into the lDR 7 will be executed by amicroprogram contained in the first set of microprograms since thelocation of the first microprogram statement will be contained in thememory segment corresponding to the code 5,.

The above discussion has disclosed a microprogrammed computer in whichthe execution characteristics of program instructions can be changed byexecuting a selected program instruction. In view of the discussionabove many variations in implementation of applicant's invention, withinthe spirit and scope of applicants invention, will become clear to thoseskilled in the art.

What is claimed is:

1. In a digital computer, the combination comprising:

a microprogram memory comprising a plurality of storage locations forstoring a corresponding plurality of microprogram statements, eachstorage location comprising means for storing any one ofa plurality ofmemory segment codes, each memory segment code uniquely identifying aplurality of said storage locations;

selection means, connected to said microprogram memory, for generatingsignals for accessing the microprogram statement stored in any selectedstorage location;

a register connected to said microprogram memory and comprising meansfor storing the memory segment code comprising the microprogramstatement last accessed by said selection means;

a program memory for storing program instructions, each comprising anyone ofa plurality of operation codes;

wherein said register is further connected to said program memory andfurther comprises means for storing any one of said operation codes, theoperation code stored identifying a corresponding storage location ofthe plurality of storage locations identified by the memory segment codestored in said register;

wherein said selection means is connected to said register; and

wherein said selection means responds to the memory segment code and theoperation code stored in accessed. 2. In a digital computer responsiveto programs com- 5 prising any one or more ofa set of programinstructions and a selected program instruction, the combinationcomprising:

a memory means, comprising storage locations, for storing a first and asecond set of microprograms, each of said sets comprising a microprogramcorresponding to each ofsaid program instructions, each microprogramconsisting of one or more microprogram statements, each microprogramstatement comprising any one of a plurality of memory segment codes,each memory segment code uniquely identifying a group of said storagelocations;

wherein for each program instruction of said set of program instructionsthe memory segment code comprising the final microprogram statement inthe corresponding microprogram of said first set of microprograms is afirst memory segment code;

wherein for said selected program instruction the memory segment codecomprising the final microprogram statement in the correspondingmicroprogram of said first set of microprograms is a second memorysegment code;

wherein for each program instruction of said set of program instructionsthe memory segment code comprising the final microprogram statement inthe corresponding microprogram of said second set of microprograms issaid second memory segment code;

wherein for said selected program instruction the memory segment codecomprising the final microprogram statement in the correspondingmicroprogram of said second set of microprograms is a third memorysegment code;

selection means, connected to said memory means.

for generating signals for selecting the microprogram statement storedin any one of said storage locations; and

storage means connected to said memory means for storing in a firstfield the memory segment code comprising the microprogram statement lastselected by said selection means.

3. The combination of claim 2 wherein said third memory segment code isidentical to said second memory segment code.

4. The combination of claim 3 wherein said selection means is furtherconnected to said storage means and is responsive to the memory segmentcode stored in said first field for generating said signals.

signals.

t 0 l 'l l

1. In a digital computer, the combination comprIsing: a microprogrammemory comprising a plurality of storage locations for storing acorresponding plurality of microprogram statements, each storagelocation comprising means for storing any one of a plurality of memorysegment codes, each memory segment code uniquely identifying a pluralityof said storage locations; selection means, connected to saidmicroprogram memory, for generating signals for accessing themicroprogram statement stored in any selected storage location; aregister connected to said microprogram memory and comprising means forstoring the memory segment code comprising the microprogram statementlast accessed by said selection means; a program memory for storingprogram instructions, each comprising any one of a plurality ofoperation codes; wherein said register is further connected to saidprogram memory and further comprises means for storing any one of saidoperation codes, the operation code stored identifying a correspondingstorage location of the plurality of storage locations identified by thememory segment code stored in said register; wherein said selectionmeans is connected to said register; and wherein said selection meansresponds to the memory segment code and the operation code stored insaid register to generate signals defining the storage location storingthe microprogram statement to be accessed.
 2. In a digital computerresponsive to programs comprising any one or more of a set of programinstructions and a selected program instruction, the combinationcomprising: a memory means, comprising storage locations, for storing afirst and a second set of microprograms, each of said sets comprising amicroprogram corresponding to each of said program instructions, eachmicroprogram consisting of one or more microprogram statements, eachmicroprogram statement comprising any one of a plurality of memorysegment codes, each memory segment code uniquely identifying a group ofsaid storage locations; wherein for each program instruction of said setof program instructions the memory segment code comprising the finalmicroprogram statement in the corresponding microprogram of said firstset of microprograms is a first memory segment code; wherein for saidselected program instruction the memory segment code comprising thefinal microprogram statement in the corresponding microprogram of saidfirst set of microprograms is a second memory segment code; wherein foreach program instruction of said set of program instructions the memorysegment code comprising the final microprogram statement in thecorresponding microprogram of said second set of microprograms is saidsecond memory segment code; wherein for said selected programinstruction the memory segment code comprising the final microprogramstatement in the corresponding microprogram of said second set ofmicroprograms is a third memory segment code; selection means, connectedto said memory means, for generating signals for selecting themicroprogram statement stored in any one of said storage locations; andstorage means connected to said memory means for storing in a firstfield the memory segment code comprising the microprogram statement lastselected by said selection means.
 3. The combination of claim 2 whereinsaid third memory segment code is identical to said second memorysegment code.
 4. The combination of claim 3 wherein said selection meansis further connected to said storage means and is responsive to thememory segment code stored in said first field for generating saidsignals.
 5. The combination of claim 4 further comprising: programmemory for storing said programs; wherein each of said programinstructions comprising said programs comprises any one of a pluralityof operation codes; wherein said storage means is further connected tosaid program memory for storing in a second field any one of saidoperation codes; and wherein said selection means connected to saidStorage means is further responsive to the operation code sotred in saidsecond field for generating said signals.